搜索资源列表
Fifo
- 一个FIFO源代码，基于Altera FPGA-A FIFO source code, based on Altera FPGA
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
usb_blaster
- 文件列表(日期：2005080604~2009101613)
VIDEO-FPGA
- 视频采集输出实例，FPGA视频采集和输出-Video Capture output examples
DE2_70_TV
- --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor shoul
2
- CCD信号采集系统的USB接口设计,CCD信号采集系统的USB接口设计-vhdl
T2_USB_IN
- 这是一段关于USB接口输入的VHDL源程序-S9_LED_RUN.rar
thesis_all
- VHDl code for USB microcontrolel
DE2_TV
- 友晶公司DE2开发板的TV示例完整源代码 FPGA Cyclone-Friends of the crystal of TV company DE2 development board complete source code for FPGA CycloneII sample
usb_in
- usb输入驱动，硬件描述语言VHDL，代码简洁，实现功能完善-usb input drivers, hardware descr iption language VHDL, the code simple, to achieve functional. .
usb_out
- usb输出驱动，硬件描述语言VHDL，代码简洁，功能完善-usb output driver, hardware descr iption language VHDL, the code simple and functional. . .
z80control_latest.tar
- z80控制器,内部包含VHDL源代码,FOF文件,基于USB借口的设计实例等.-z80 controller contains the VHDL source code inside, FOF files, USB-based design example of such an excuse.
Asynchronous_slavefifo.v
- data trasfer from fpga to usb device developed in vhdl format
usb11_phy_translation_latest.tar
- USB1.1 物理层实现 VHDL，opencore上也是可以下载的，是1.1的版本，比较简单，但是很实用，对于入门usb还是有帮助的-usb11_phy_translation_latest version
ISE_lab5
- 使用VHDL 语言编写7 段数码管显示程序， 掌握数码管的驱动方法。使用USB 电缆或并口下载线下载逻辑电路到FPGA，并 调试电路使其正常工作。-Using the VHDL language 7-segment display program, for digital control of the driving method. Using the USB cable or parallel port download cable to download logic to FPGA,
usb_FPGA
- USB的FPGA控制程序，用VHDL编写，还包括一些参考资料，具有一定的参考价值。-USB-FPGA control program, written in VHDL, with some reference value.
jibenmendianlu
- 熟悉使用 ISE 软件进行简单的VHDL 文本方式设计，学习使用USB 电缆或并口下载线 下载逻辑电路到FPGA，并能调试电路使其正常工作。熟悉数字电路集成设计的过程。-Familiar with ISE software to design a simple VHDL text, learning to use a USB cable or parallel port download cable Download logic to the FPGA, and can debug t
duolufuyongqi
- 1. 学习使用 ISE 软件，并用VHDL 语言设计多路复用器； 2. 使用 USB 电缆下载逻辑电路到FPGA，并能根据电路原理调试电路使其正常工作； 3. 掌握数字电路集成设计的过程-1 Learn to use ISE software, and design using VHDL language multiplexer (2) using a USB cable to download logic to the FPGA, and debug circuit accor